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Influence of gate-source/drain misalignment on the performance of bulk FinFETs by a 3D full band Monte Carlo simulation
用三维蒙特卡罗模拟栅-源/漏不对准对体硅FinFET器件性能的影响

Keywords: bulk FinFET,gate-source/drain misalignment,3D Monte Carlo simulation,carrier transport
体硅FinFET
,栅-源/漏不对准,三维蒙特卡罗模拟,载流子输运

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Abstract:

We investigate the influence of gate-source/drain (G-S/D) misalignment on the performance of bulk fin field effect transistors (FinFETs) through the three-dimensional (3D) full band Monte Carlo simulator. Several scattering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.

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